Semiconductor device manufacturers fabricate integrated circuit ("IC") chips by printing many dies on a semiconductor wafer. Both during and following fabrication, a semiconductor chip manufacturer will test the integrated circuit chips to determine that it satisfies design specifications. Known semiconductor wafer testing methods are time consuming, because the manufacturer typically tests each integrated circuit chip one after the other to determine whether the integrated circuit chip satisfies design electrical connectivity, electronic functionality and performance requirements.
These processes involve placing a test probe in electrical contact with an integrated circuit chip to send and receive test signals from a test control unit. Once the test control unit fully tests the integrated circuit chip, the probe moves to the next integrated circuit chip on the wafer. The number of test probe movements necessary to test the tens or perhaps hundreds of integrated circuit chips on a single semiconductor wafer make testing time constitute a significant portion of integrated circuit chip fabrication costs. For example, in many integrated circuit memory chip manufacturing processes, as much as 25-30% of the processing costs relate to integrated circuit chip testing at the one megabyte level of integration. With more complex integrated circuit chip circuits, testing costs can be even higher. If a testing method or apparatus could significantly reduce the speed of integrated circuit chip testing, then this percentage of processing costs could drastically reduce. Thus, there is a need for a more rapid method of testing integrated circuit chips on a semiconductor wafer.
In an effort to decrease the time of testing integrated circuit chips on the same semiconductor wafer, some manufacturers use two or more test probes to simultaneously test two or more integrated circuit chips at a time. While this increases, to some degree, the integrated circuit chip testing speed, this method suffers from several limitations. For a number of reasons, a known multiple probe heads method can use no more than eight test probes at a time. Therefore, only as much as an eight-fold increase in speed is achievable using multiple test probe heads.
Another multiple probe limitation resides in the fact that known test probes contain no remote data processing or storage capability. Because all data processing and test control capability for integrated circuit chip testing resides with the test control unit, in known test methods a test control unit can only control one test head at a time. Consequently, if a semiconductor device manufacturer desires to use the method of testing two integrated circuit chips at one time, then two testing computers are necessary. integrated circuit chip test control computers are expensive machines to purchase and operate, so purchasing multiple test control computers to test additional integrated circuit chips simultaneously generally is not cost effective. A need exists, therefore, for an economical method and apparatus to test a plurality of integrated circuit chips without the additional need of multiple testing control units.
Another limitation in conventional integrated circuit chip testing methods relates to wire bonding techniques that known test probes employ. Conventional test probes mount to an epoxy board that has lead wires to electrically connect the test probe to test control unit hardware. The lead wires bond to the epoxy board and connect to metal pins on the test probe. The metal pins engage "pads" on the integrated circuit chip. Each of the integrated circuit chips pads provides a connection for an integrated circuit chip power or signal input or output. There are practical limits to the size and number of lead wires that an integrated circuit test probe can contain. For example, a typical integrated circuit memory chip uses between 20 and 40 pads. Therefore, the test head must include between 20 and 40 lead wires for each integrated circuit chip it will test. If a semiconductor wafer contains as many as 300 typical integrated circuit memory chips, for example, then the test probe must have as many as 9,000 lead wires (=300 chips.times.30 lead wires/chip) bonded to the epoxy board and running between the test probe pins and the test control unit contacts.
This requirement far exceeds the epoxy board wire bonding process technique capabilities that conventional test probe heads employ. If a way existed to avoid this test probe lead wire problem, then a manufacturer may address more effectively the other problems relating to increasing integrated circuit chip testing speed. Thus, there is a need for an integrated circuit chip testing method and apparatus that more effectively permits testing multiple integrated circuit chips on a single semiconductor wafer without their lead wire design problem.
Yet another limitation respecting known test devices is that with conventional probe head structures signal propagation speeds are limited due to large inductance of the probe wires. This limitation further restrains the multiple integrated circuit testing. If manufacturers desire to increase integrated circuit testing speed, this limitation must be overcome. Thus, there is a need for a method and apparatus can test many integrated circuits at one time without the speed restrictions from lead wire impedence.